1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method and, more particularly, to a device structure and its manufacturing method for reliably making a contact connecting a metal wiring layer formed in an upper level of a capacitor of DRAM to an impurity diffusion layer and a gate electrode formed on a semiconductor substrate without increasing the junction leakage.
2. Description of the Related Art
A conventional LSI device incorporating DRAM cells and logics is explained below with reference to FIGS. 1, 2, 3A and 3B.
FIG. 2 is an enlarged cross-sectional view of a single MOS transistor and a portion around it. As shown in FIG. 2, a contact hole 94 is formed on a semiconductor substrate 91 to connect a metal wiring layer (not shown) formed in an upper level of a DRAM cell to an impurity diffusion layer 93 and a gate electrode 92 formed on the semiconductor substrate 91. For making a high-density structure, a capacitor of a DRAM memory cell must be high in dimension in order to keep a large capacity without increasing the area occupied by the capacitor. For this purpose, a very deep contact has to be made, requiring a long etching process. During a long etching process, the contact hole 94 is liable to be excessively etched.
As shown in FIG. 2, aspect ratio of the contact hole 94 (“depth of the contact” to “diameter of the contact hole”) is 5 to 10, and it is very difficult to make it without undesirably etching the impurity diffusion layer 93 and a device isolation film (not shown) of the semiconductor substrate 91. At worst, an aperture is made beyond the junction interface, inviting an increase of the junction leakage.
Taking it into consideration, Japanese Patent Laid-Open Publication No. Hei 10-79430 discloses a technique, as an improvement, which makes an impurity diffusion layer by making a silicon nitride film as an etching stopper layer in a contact opening on a semiconductor substrate, without scraping it, and thereby prevents an increase of the junction leakage.
On the other hand, as shown in FIG. 1, in an LSI device incorporating DRAM cells and logics, it is not possible to keep a large margin for facilitating alignment between the impurity diffusion layer 93 and the contact hole 94 connected thereto. Thus, as shown in FIG. 1, the contact hole 94 might open at the boundary between the impurity diffusion layer 93 and a device isolation insulating film 95.
In this case, if the etching stopper layer formed just above the impurity diffusion layer 93 does not have a sufficient thickness, the device isolation insulating film 95 will be also etched. And, if it is etched deeply beyond the surface of the impurity region, it causes junction leakage. In order to prevent junction leakage, a thick etching stopper has to be made.
However, as shown in FIGS. 3A and 3B, if the etching stopper layer 96 is thick, it invites generation of a void (empty space) 98 in an inter-layer insulating film 97 stacked later. Alternatively, if a nitride film is used as the etching stopper film 96, it results in increasing the inter-wiring capacitance as much as its high dielectric constant, and ultimately prevents improvement of the device speed. FIGS. 3A and 3B are diagrams explaining problems involved in the conventional technique, and they schematically show cross-sectional configurations of a major part of the device.
As shown in FIG. 3A, insulating film side walls 910 are formed at opposite sides of each gate electrode 99. If the etching stopper film (silicon nitride film) 96 formed thereafter over the entire surface is thin, the space between gate electrodes can be readily buried by ordinary CVD (chemical vapor deposition). Also when the inter-layer insulating film 97 is formed above the etching stopper film, ample space remains between the gate electrodes 99.
However, in the case where the thickness of the etching stopper film 96 is increased as shown in FIG. 3B for the purpose of enhancing its function, the gap between the gate electrode 99 is extremely narrowed like a slit. Therefore, when the inter-layer insulating film 97 is made later by CVD, a void 98 is produced, and the gap cannot be buried even by a heating reflow technique. Once a void 98 is made in the inter-layer insulating film 97 due to a thick etching stopper film 96, poly-silicon electrodes in self-aligned contact portions in DRAM cells are short-circuited via the void 98, seriously degrading the production yield.
Although the earlier Japanese Patent Laid-Open Publication No. Hei 10-79430 does not teach making the etching stopper layer 96 as an intermediate layer of the inter-layer insulating film 97, Japanese Patent Laid-Open Publication No. Hei 7-13087 discloses a technique for making a stopper layer against isotropic etching conducted upon making a cylinder-type capacitor. By combining these two earlier techniques, it would be easy to invent making an etching stopper layer as an intermediate layer. However, there is no teaching about a multi-layered configuration of the etching layer, and even if it is merely divided into two layers, when the lowest first etching stopper layer is thick, voids are produced in the above-mentioned DRAM-cell burying process, e.g, upon making an inter-layer insulating film.